Digital Design Verification Engineer (ASIC)

Digital Design Verification Engineer Contract Location: Poland Contract Terms * Length: 6 Months Initial * Rate: Of project budget * Working Arrangement: Hybrid (Mostly Remote, occasional site visits) * Start Date: ASAP Essential Skills * Strong SystemVerilog * Proven experience with UVM * UVM testbench development from scratch * Testbench architecture, stimulus generation, monitors, scoreboards * Functional coverage definition and closure * Verification of complex digital IP/SoC blocks Desirable Skills * USB experience (highly desirable but not essential) * Exposure to high-speed interfaces or complex protocols * Experience working close to RTL teams Desirable Mixed Profile Skills Candidates with a mixed design/verification background are also of interest, provided verification skills are present: * RTL exposure in Verilog / SystemVerilog * Ability to read, understand, and occasionally modify RTL * Experience collaborating on design-for-verification activities Additional Nice-to-Haves * RS FEC exposure * Experience in verification planning and execution ownership * Comfortable working in an international, distributed team